Project

Define the control intent, target board, and scan behavior.

Production readiness

0%workflow complete

Workflow status

Project identity

PROJECT NAME

DESCRIPTION

AUTHOR

REVISION

Execution profile

ARDUINO BOARD

SCAN MODE

SCAN INTERVAL (ms)

OUTPUT STARTUP DEFAULT

DIGITAL DEBOUNCE (ms)

SAFE STARTUP HOLD (ms)

Filter digital inputs with non-blocking debounce

Include serial diagnostics in generated code

Generated sketches use a process image, safe startup hold, optional debouncing, scan-overrun accounting, and non-blocking timing.

Synchronization

AUTHORITATIVE SOURCE

Ladder authority regenerates code from the model. Code authority parses the supported Arduino subset. Manual mode preserves edits and shows differences.

Logic Model schema2.9

Stable element IDsEnabled

Offline persistencelocalStorage

Project health

I/O Map

Assign symbols to board pins and physical devices.

Symbol	Pin	Category	Direction	Data	Pull-up	Active	Initial	Description / Device	Actions

Pin conflicts and invalid board assignments are detected in Verify. Internal relays and variables do not require a physical pin.

Ladder Editor

Build synchronized control logic on a valid rung grid.

Arduino Code

Generate readable sketches or parse the supported PLC-style subset.

Synchronization control

No synchronization analysis yet.

Source map and generator manifest

Simulator

Execute the Logic Model top-to-bottom without physical hardware.

Input forcing

Timers and counters

No timer or counter resources.

Scan status

StateSTOPPED

Scan0

Last duration0.00 ms

Interval20 ms

Live ladder

Test Bench

Run repeatable input sequences against expected outputs.

Verification

Find model, pin, conversion, and control-semantic problems.

Summary

Conversion confidence

Overall100%

Converted rungs0

Unsupported sections0

Generator preflight

Safety checks

RUNGWRIGHT detects suspicious naming and logic patterns, but cannot certify machinery safety.

Diagnostics

Export

Package the synchronized engineering record.

Project JSONComplete Logic Model, I/O, tests, diagnostics, and source mapping.

Arduino sketchGenerated .ino using the selected board and scan architecture.

Ladder SVGPrint-friendly vector diagram with rung comments and IDs.

Ladder PNGRaster preview generated locally from the SVG.

I/O map CSVPin assignments, device descriptions, defaults, and safety notes.

Test results CSVExpected and actual values with pass/fail results.

Engineering reportPrintable HTML report with project, I/O, ladder, code, diagnostics, and sign-off.

Evidence package ZIPUncompressed browser-generated ZIP containing the principal artifacts.